1. Field of the Invention
The invention generally relates to phase-lock bops (PLL) and in particular to digital phase-lock bops for use in connection with a microprocessor chip.
2. Description of Related Art
Digital PLL's are being increasingly employed in connection with microprocessor chips, in particular for maintaining and regenerating a clock signal used by the microprocessor chip. Initially, such PLL's were fabricated with components separate from the microprocessor chip with appropriate interconnection circuitry provided for operably connecting the off-chip PLL components to the microprocessor chip. Although an off-chip configuration has been successful for relatively low frequency microprocessor chips, such a configuration is not particularly effective for high frequency microprocessor chips, in part, due to noise occurring during transmission of signals between the microprocessor chip and the off-chip PLL components. Furthermore, a PLL having off-chip components incurs additional costs resulting from the fabrication and assembly of the off-chip components, as well as the provision of an extra pin for allowing communication between the microprocessor chip and the off-chip PLL components.
Accordingly, it is desirable to provide a complete PLL directly on a microprocessor chip, whereby the noise problem and extra costs described above are largely eliminated. FIG. 1 illustrates a portion of a PLL circuit appropriate for integrating within a microprocessor chip. For clarity and brevity the microprocessor chip itself is not illustrated in FIG. 1.
PLL circuit 10 of FIG. 1 includes a phase-and-frequency detector (PFD) 12, a charge pump (CP) 14, a voltage controlled oscillator (VCO) 16, a resistor 18 and a capacitor 20. PFD 12 receives a digital reference signal along an input line 22 and a digital feedback signal along an input line 24. PFD 12 is a digital circuit which generates signals representative of phase or timing differences between the feedback signal received along line 24 and the reference signal received along line 22. If the feedback signal has a phase later than that of the reference signal, PFD 12 outputs an UP signal along output line 26 which is representative of the amount of phase difference between the reference signal and that of the feedback signal. More specifically, the UP signal is a digital pulse having a length proportional to the phase difference between the feedback signal and the reference signal. If the feedback signal has a phase earlier than that of the reference signal, PFD 12 outputs a DOWN signal along an output line 28 which is representative of the amount by which the phase of the feedback signal differs from that of the reference signal. As with the UP signal, the DOWN signal is a signal pulse having a length proportional to the phase difference between the feedback signal and the reference signal. Thus, the UP signal represents the amount by which the feedback signal must be advanced relative to the reference signal whereas the DOWN signal represents the amount by which the feedback signal must be delayed relative to the reference signal.
CP 14 receives the UP and DOWN signals along lines 26 and 28 respectively. An output of the CP 14 is connected along a signal line 30 to an input of VCO 16 as well as into capacitor 20 through resistor 18. As can be seen from FIG. 1, resistor 18 and capacitor 20 are connected in series between a ground and signal line 30. Resistor 18 operates as a damping resistor for damping the overall frequency lock and for controlling the gain of the phase-lock of the PLL. CP 14 controls the amount of charge contained within capacitor 20 in response to the UP and DOWN signals received from PFD 12. More specifically, if the UP signal is active, CP 14 outputs current to capacitor 20 to increase the amount o: charge stored by capacitor 20. If the DOWN signal is active, CP 14 withdraws charge from capacitor 20 to decrease the amount of charge contained therein.
Hence, the amount of charge stored within capacitor 20 depends upon the historic or integrated difference between the feedback signal and the reference signal. A voltage sensed by VCO 16 likewise depends upon the difference between the frequency of the reference signal and the feedback signal because VCO 16 is electrically connected to capacitor 20 through resistor 18. VCO 16 includes two analog circuit components, a voltage-to-current circuit (VTCC) 32 and a current-controlled oscillator (CCO) 34. VTCC 32 generates a current signal proportional to a voltage carried on line 30. CCO 34 converts the current signal output by VTCC 32 into an output frequency signal for transmission along output signal line 36.
Although not shown in FIG. 1, output line 36 is connected through portions of the microprocessor chip in a feedback loop ultimately connected to feedback input line 24. The circuitry illustrated in FIG. 1 and the feedback loop (not shown) together provide the entire PLL. As can be appreciated, the output signal along line 36 has a frequency controlled by differences detected between the frequencies of the reference signal and the feedback signal. Output signal 36 may be connected to a clock signal line to regenerate a clock signal used for the synchronizing operation of the microprocessor chip.
The PLL circuit of FIG. 1 is fabricated according to conventional complementary metal oxide semiconductor (CMOS) technology. Hence, the size of capacitor 20 is restricted due to the limitations of CMOS capacitor fabrication. Because of the restriction in the size of the capacitor, the overall gain of the PLL illustrated in FIG. 1 is relatively high, requiring extremely high resistance values for damping resistor 18. As noted above, the damping resistor 18 operates to both damp the frequency lock and control the gain of the overall phase lock. As a result, mutually exclusive demands are imposed on the resistance value of resistor 18. The resistance value should be large to properly damp the frequency lock but must be relatively small to properly damp the phase lock. As can be appreciated, compromises must be made to accommodate the conflicting demands upon the resistor, resulting in a damping resistor which is only marginally effective in damping both the frequency lock and the phase lock.
Moreover, in most fabrication processes for fabricating a damping resistor on a microprocessor chip, the resistor is fabricated out of MOS transistors such that the resistance value of the resistor varies according to process and operating conditions. Hence, the resistance value cannot be precisely and repeatable defined. Furthermore, the phase gain of the PLL varies with operating frequency and conditions. As a result of these various restrictions and other factors, a typical on-chip PLL, such as illustrated in FIG. 1, provides inadequate damping for frequency lock. Further, the amount by which the PLL is under-damped varies from chip-to-chip as a result of processing and operating conditions. The various disadvantages are more significant for microprocessor chips operating at high frequencies.